LZRW3 Compression Core

AltraCores LZRW3 Core implements Ross Williams’ LZRW3 algorithm, enabling a state of the art FPGA or ASIC solution for wire-speed, lossless data compression and decompression. The AltraCores implementation is a standalone soft IP core that performs the compression and expansion functions with higher speed and throughput than software.

AltraCores LZRW3 Cores come complete with:

  • Verilog RTL source code
  • Verilog test bench and test scripts
  • Synthesis and timing constraints
  • Optional C and System C model
  • Optional aggregation interface wrapper



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