News and Media

January 24, 2012
Optimizing WAN Throughput With Compression
by Hank Cohen, Director of Product Management at Altior Inc.

October 20, 2011
Watch Altior, Inc. at the SDC Event
Altior's Shirish Phatak discusses a lightweight layered compressed file system,

September 28, 2011
Compression-Decompression File System Accelerator
StorageNewsletter.com

September 20, 2011
Storage Developer Conference
Shirish Phatak, Vice President of Technology Speaks at the Storage Developer Conference.
Topic: "A Lightweight Layered Compressed File System with Hardware Acceleration"
2:00 PM – 2:50 PM
Hyatt Regency Hotel
Santa Clara, CA

6/24/2010
EE Times Virtual Conference: Maximizing the Flexibility of FPGAs
Panel Discussion: FPGA Processing Sweet Spots...
(CebaTech is a featured panelist along with Actel, ARM, and Xilinx)

06/16/2010
Chip Estimate catches up with Joe Rash, CebaTech's Vice President of Business Development
(Video interview discussing GZIP IP and its uses in the industry)

04/27/2010
CebaFlex FPGA-based subsystem boards boost protocol processing up to 10x
Embedded.com - The Official Site of the Embedded Development Community

04/26/2010
CebaTech Launches New CebaFlex FPGA-Based Board-Level Protocol Acceleration Subsystems
EDA Cafe

04/26/2010
CebaTech rolls protocol acceleration subsystems
EETimes

03/03/2010
The importance of FPGA-to-ASIC solutions to accelerate CPU-based protocols
Embedded.com - The Official Site of the Embedded Development Community

01/22/2010
Encryption and Compression for Enterprise Storage Solutions
Computer Technology Review

07/29/2009
What is the future for Intellectual Property?
EDN: Information, News, & Business Strategy for Electronics Design Engineers

07/22/2009
The business of IP: it ain't a bake sale
EDA DesignLine

07/16/2009
The best ever DAC standards booth
Synopsys

04/17/2008
C-based coprocessor design, Part 1: SIMD architecture
DSP DesignLine

04/17/2008
C-based coprocessor design, Part 2: Datapath customization
DSP DesignLine

01/27/2008
Verification — the Next Step for ESL
Chip Design Magazine

06/21/2007
High-Value Networking and Data Storage IP Demands Dramatically New Approach to IP Creation
Chip Design Magazine

5/15/2007
Efficient high-speed compression/decompression for FPGAs and ASICs
Clive Maxfield, Programmable Logic Design Line
Cebatech's easy-to-integrate GZIP family of CebaIP cores provides hardware compression and decompression for data and storage networking FPGAs and ASICs.

05/09/2007
Compression/decompression tradeoffs for data networking and storage
Chad Spackman, CebaTech, Inc., Network Systems Design Line
Several design trade-offs to exist when building a high performance lossless data compression engine. Each of these trade-offs can vary the gate area of the end design greatly and have significant impact on the overall efficiency of the compressor (compression ratio).