News and Media

January 24, 2012
Optimizing WAN Throughput With Compression
by Hank Cohen, Director of Product Management at Altior Inc.

October 20, 2011
Watch Altior, Inc. at the SDC Event
Altior's Shirish Phatak discusses a lightweight layered compressed file system,

September 28, 2011
Compression-Decompression File System Accelerator

September 20, 2011
Storage Developer Conference
Shirish Phatak, Vice President of Technology Speaks at the Storage Developer Conference.
Topic: "A Lightweight Layered Compressed File System with Hardware Acceleration"
2:00 PM – 2:50 PM
Hyatt Regency Hotel
Santa Clara, CA

EE Times Virtual Conference: Maximizing the Flexibility of FPGAs
Panel Discussion: FPGA Processing Sweet Spots...
(CebaTech is a featured panelist along with Actel, ARM, and Xilinx)

Chip Estimate catches up with Joe Rash, CebaTech's Vice President of Business Development
(Video interview discussing GZIP IP and its uses in the industry)

CebaFlex FPGA-based subsystem boards boost protocol processing up to 10x - The Official Site of the Embedded Development Community

CebaTech Launches New CebaFlex FPGA-Based Board-Level Protocol Acceleration Subsystems

EDA Cafe

CebaTech rolls protocol acceleration subsystems


The importance of FPGA-to-ASIC solutions to accelerate CPU-based protocols - The Official Site of the Embedded Development Community

Encryption and Compression for Enterprise Storage Solutions

Computer Technology Review

What is the future for Intellectual Property?

EDN: Information, News, & Business Strategy for Electronics Design Engineers

The business of IP: it ain't a bake sale

EDA DesignLine

The best ever DAC standards booth


C-based coprocessor design, Part 1: SIMD architecture

DSP DesignLine

C-based coprocessor design, Part 2: Datapath customization

DSP DesignLine

Verification — the Next Step for ESL

Chip Design Magazine

High-Value Networking and Data Storage IP Demands Dramatically New Approach to IP Creation

Chip Design Magazine

Efficient high-speed compression/decompression for FPGAs and ASICs

Clive Maxfield, Programmable Logic Design Line
Cebatech's easy-to-integrate GZIP family of CebaIP cores provides hardware compression and decompression for data and storage networking FPGAs and ASICs.

Compression/decompression tradeoffs for data networking and storage

Chad Spackman, CebaTech, Inc., Network Systems Design Line
Several design trade-offs to exist when building a high performance lossless data compression engine. Each of these trade-offs can vary the gate area of the end design greatly and have significant impact on the overall efficiency of the compressor (compression ratio).


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  • Optimizing WAN Throughput With Compression by Hank Cohen, Director of Product Management at Altior Inc.

    by Altior Inc. Thursday, 02 February 2012 21:18

  • Altior Inc. Appoints Byron Rashed as Director of Marketing and PR & Hank Cohen as Director of Product Management

    by Altior Inc. Tuesday, 15 November 2011 22:58

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