Overview

Electronic Design Automation (EDA) is largely about saving time in the development of electronic designs. EDA tools strive to reduce verification time, design cycle time, and time to market. It's commonly understood that design cycles must continue to shrink due to market pressures, and that design verification is a bottleneck in today's design cycle. In fact, improving verification throughput within existing resources represents one of the biggest challenges facing contemporary hardware developers and the EDA tools industry. The feasibility of increasingly complex systems in silicon is not matched by an ability to guarantee the functional correctness of a design.

The Electronic System Level (ESL) tools segment of the EDA industry attempts to address the challenge of improving verification throughput by moving up in levels of design abstraction and targeting the front end of the design process. Tools from multiple vendors of varying perspectives focus on modeling, design exploration, and better design description to eliminate error early in the design process. Typically the solutions are limited to only one or two steps of the process — tools may support architectural exploration or design implementation, but not both; or they may support design entry or design verification, but not both. The result is a fragmented design flow that forces design teams to invent project-specific methods and that continues to rely on RTL simulation for verification.

Resource and time-intensive RTL simulation is the key challenge to breaking the verification bottleneck in modern chip design. To solve the problem, CebaTech has pioneered a different approach to ESL in which untimed ANSI C is the design language, architecture is explored and implemented in the C source, verification takes place in the native C software environment, and synthesizable Verilog RTL is automatically generated. And simulation becomes an optional secondary check in device verification.

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