Careers

Job Description

Title: RTL Designer
Reports to: VP of Operations
Location: NJ Corporate HQ
Travel: Not Required

As an engineering team member, you will contribute to the design, development and verification of Altior's range of hardware protocol acceleration solutions for data networking and enterprise storage applications.

Responsibilities

• Lead the block level architecture design.
• Author detailed design documents.
• Develop and execute thorough design, simulation, implementation and lab verification.
• Participate in synthesis, static timing analysis, DFT.
• Assist in the development of embedded FW.

Qualifications

• BSEE with 7+ (or MSEE with 5+) years related experience.

Experience

• Excellent knowledge of communication systems and high speed digital circuit design.
• Strong analytical, and problem solving skills as well as hands-on lab debugging skills.
• Excellent knowledge of RTL design, simulation and synthesis.
• System Verilog and assertion based verification background a plus.
• Good Knowledge in languages relevant to the ASIC/FPGA development process including Verilog, Unix Scripting, and C.
• Working experience needs to demonstrate the technical expertise in successful completion of multiple ASIC/FPGA projects.
• Self-motivated, excellent communication skills and ability to excel in a team environment.

Company Description

Altior Inc. is a fast-growing startup that migrates CPU-intensive algorithms including Compression, Encryption, Hashing, and customer-specific algorithms, to a PCIe acceleration card or an ASIC. The company is an end-to-end solution supplier including the hardware, algorithm IP, SW Drivers, and integration tools to deliver very fast and very low-risk complete solutions for OEM customers.

To Apply:

Submit resume and cover letter to  This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

No third party applications