Papers

Considerations for Building a High Performance Hardware Compression/Decompression Engine

…Hardware compression offers a significant improvement in the rate at which data can be compressed and decompressed. For example, benchmarks of the popular GZIP data compression routine on an 3Ghz Pentium class CPU result in maximum data rates of approximately 200Mb/s. In comparison, hardware compression can achieve data rates of 2Gb/s or greater. With a 10X or more speedup in compression processing, it's clear that dedicating a hardware engine or co-processor to perform this function will result in much greater performance. To read more, click here.

An Electronic System Level Methodology that Dramatically Shortens the Design Cycle for Complex Chip Designs

CebaTech is pioneering a different approach to ESL-based design in which untimed ANSI C is the design language, architecture is explored and implemented in the C source, verification takes place in a pure C software environment, and synthesizable Verilog RTL is automatically generated. The result is a flow that dramatically shortens the development time for complex chips- whether they be SoC, ASIC or FPGA based designs. In addition, by enabling software algorithms to be implemented in dedicated hardware, lower cost, and lower power chips can be produced. To read more, click here.

AES Advanced Encryption Test Case

The Advanced Encryption Standard (AES) algorithm presented in this paper illustrates the ease of adoption and productivity benefits of CebaTech's C2R Compiler™ and C-based hardware design flow for Electronic System Level (ESL) design.

CebaTech's methodology puts the power in the hands of the architect/designer by defining hardware architecture in the C source code. For the AES test case, various architectural changes (performance and area optimizations) were made in a matter of hours/days, allowing extensive exploration of design trade-offs in a short period of time. By embracing untimed ANSI C as the hardware description language, the CebaTech flow delivers a 3-5x productivity gain when compared to traditional Verilog or VHDL RTL hand-coding techniques. Extensive ANSI C syntax support means that existing C code bases can be compiled with minimal changes to the source, and programmers can take advantage of the full power of the C language. To read more, click here.

An IEEE 754 Floating Point Engine designed with an Electronic System Level Methodology

This paper presents the design and implementation of an IEEE 754-compliant, single-precision, coarse-level pipelined floating point engine designed using a new electronic system level (ESL) tool. The starting point was the SoftFloat ANSI C implementation of the standard. Minimal modifications, in the form of two parallel processes, were introduced to map the ANSI-C code to the input/output interface of a CardBus-based field-programmable gate array (FPGA) prototyping board. The remaining part of the code was directly synthesized to gates using CebaTech's C2R Compiler™ and a number of configurations were studied with various degrees of functional unit sharing and capabilities. To read more, click here.