In The News

Articles

04/17/2008
C-based coprocessor design, Part 1: SIMD architecture
DSP DesignLine
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04/17/2008
C-based coprocessor design, Part 2: Datapath customization
DSP DesignLine
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01/27/2008
Verification — the Next Step for ESL
Chip Design Magazine
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06/21/2007
High-Value Networking and Data Storage IP Demands Dramatically New Approach to IP Creation
Chip Design Magazine
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5/15/2007
Efficient high-speed compression/decompression for FPGAs and ASICs
Clive Maxfield, Programmable Logic Design Line
Cebatech's easy-to-integrate GZIP family of CebaIP cores provides hardware compression and decompression for data and storage networking FPGAs and ASICs. » more

05/09/2007
Compression/decompression tradeoffs for data networking and storage
Chad Spackman, CebaTech, Inc., Network Systems Design Line
Several design trade-offs to exist when building a high performance lossless data compression engine. Each of these trade-offs can vary the gate area of the end design greatly and have significant impact on the overall efficiency of the compressor (compression ratio). » more