“REALIZE MORE THAN 1000X SPEED-UP OF TEST FUNCTIONS AND UP TO 60% REDUCTION IN TIME TO COMMERCIAL PRODUCT WITH CEBATECH'S REVOLUTIONARY C TO RTL DESIGN FLOW”

IN THE NEWS

April 17, 2008
DSP DesignLine — C-based coprocessor design, Part 1: SIMD architecture » more

April 17, 2008
DSP DesignLine — C-based coprocessor design, Part 2: Datapath customization » more

January 27, 2008
Chip Design Magazine — Verification — the Next Step for ESL » more

June 21, 2007
Chip Design Magazine — High-Value Networking and Data Storage IP Demands Dramatically New Approach to IP Creation » more

PRESS RELEASES

May 15, 2007
CebaTech Announces GZIP Family of CebaIP Cores™ » more

May 7, 2007
CebaTech Joins Chip Estimate's Prime IP Partner Program » more

January 16, 2007
CebaTech Inc. Joins HyperTransport Technology Consortium » more