Closing the Gap / The CebaTech Advantage

Closing the Verification Gap

CebaTech's technology enables an entire SoC to be coded in C and run in a native C software environment in its source form or in cycle-accurate C form, where native execution in the software environment absolutely and precisely represents the behavior of the resultant (compiled) RTL in a simulator. CAC is compiled with a standard C compiler (e.g., gcc) and verified in the same native C environment used for the C source code. Any issues resulting from the introduction of parallelism in the structured C code can be debugged here.

CebaTech's approach to ESL is unique in that it maintains a coupling of the high level ANSI C design to the generated RTL, with the one accurately reflecting the function of the other and providing for rapid design exploration, modification, and verification, as well as design reuse. Using ANSI C software behavioral modules to make system-level trade-offs and to perform functional tests prior to committing to hardware allows a designer to achieve tremendous improvement in verification time over RTL event-based simulation.

Verification of the hardware design using RTL simulation can be replaced with much faster C/CAC testing in a native ANSI C software environment. And, once the CAC has been fully verified, it becomes the golden reference to which the generated RTL will be compared. A formal equivalence checker (EC) can then be employed to verify that the CebaTech-generated Verilog RTL is functionally equivalent to the CAC, similar in concept to the practice of verifying gate-level netlists against RTL models with EC tools. Alternatively, RTL co-simulation can also be used to verify the compiler-generated RTL.

After the RTL has been verified to be functionally equivalent to the CAC, it is ready for the standard synthesis flow to hardware implementation. The Verilog RTL code is synthesis-friendly by virtue of using one-hot state machine logic.

The CebaTech Advantage

CebaTech's C2R Compiler supports both control- and data path-dominated designs and works equally well for SoC's, FPGAs, or ASICs. By automating the development path from standard ANSI C code to synthesizable RTL, CebaTech dramatically reduces the time it takes to create, explore and implement a hardware design. By providing a direct linkage between the original design model and the final hardware instantiation, the verification of a design in the C software not only validates the functionality of the RTL, but also accelerates the verification process which, in turn, allows for more test coverage. Furthermore, CebaTech's support of the full complement function available in standard ANSI C offers the opportunity for IC design teams to derive hardware from existing, proven software with relative ease.

To learn more about CebaTech's approach to ESL and Verification, click here.