The ESL Challenge

Pioneering ESL — Taking a Software Approach to Hardware Design

As semiconductor advances have supported more complex features and systems to be realized in hardware, the design process itself has become an impediment to achieving the full application potential of modern integrated circuits (ICs). Every complex silicon development, whether system-on-chip (SoC), application specific IC (ASIC), or field-programmable gate array (FPGA) is an expensive, multi-step process with multiple opportunities for delay or failure along the way. Even so, register transfer level (RTL) continues to dominate as a hardware description language (HDL) along with RTL simulation for verification, and the combined burden grows geometrically with design scope or complexity.

“…the average team size has doubled between 2000-2006, and about 85 percent of all IC projects miss their original schedule — the average schedule slip is 44 percent… two key areas of focus for leading-edge semiconductor firms are schedule predictability and risk management of large platforms or projects.”
(Ron Collett, Numetrics Management Systems)

CebaTech's solution to the challenges of contemporary IC design, the C2R Compiler™, embraces untimed ANSI C as its HDL. A few tools using a variety of C languages have previously attempted to solve the issues of modern IC design. CebaTech's C2R Compiler deviates from those efforts in 3 important ways:

• By supporting the abstract and powerful capabilities of ANSI C, with very few exceptions
• By enabling designs ranging from small to large in scope and complexity
• By placing functional verification at the front-end of the design process and achieving 95% test coverage in the C software environment

With an equal focus on accelerating the architecture creation/exploration and the verification steps of the design process, the C2R Compiler is the first system-level tool to unify design modeling, architecture exploration, verification and implementation for full-chip design.