Data Sheets

C2R Compiler™

CebaTech's C2R Compiler is a robust behavior-level and system-level design tool that embraces untimed ANSI C as the hardware description language (HDL) to accomplish high level design abstraction. The C2R Compiler automates the development path from untimed ANSI C to synthesizable Verilog™ and delivers dramatic simulation run-time improvements that address two intertwined challenges facing semiconductor designers — growing design complexity and the increasing time and resources required for verification. READ MORE

GZIP Data Deflate Core

Multiple configuration and run-time options for CebaTech's GZIP core provide for tremendous flexibility to match the core characteristics with the user application. Configuration time options determine how the core is built, and impact performance in terms of compression, throughput and area. Run-time options determine how the core is operated, and impact performance in terms of compression ratio and throughput. These features, along with the option to tile the GZIP core to scale throughput, enable CebaTech to rapidly deliver a broad range of advanced hardware compression solutions. READ MORE

GunZip Data Inflate Core

CebaTech's family of GZIP IP cores, based upon the popular software lossless data compression algorithm, provide state of the art hardware compression and decompression to meet demanding data storage and networking needs. CebaTech hardware implementation of GunZip is in the form of a standalone soft core that performs the inflate function. CebaTech's GunZip core precisely follows the data formats specified by the deflate standard in RFC 1951 and supports frame formats for "zlib" RFC1950 and "gzip" RFC1952. Consequently it is able to decompress data previously compressed by any GZIP compliant algorithm. READ MORE