CebaRIP Cores™

CebaTech offers a full complement of standard IP cores utilized extensively by the networking and storage industries. The core competencies of the CebaTech team cover semiconductor design, design tool invention, and data networking, centered on TCP/IP and UDP protocol suite, with extensions into storage networking.

CebaTech's CebaRIP Cores™ currently include:

  • AES Core CebaTech's family of Advanced Encryption Standard (AES) IP cores, provide state of the art hardware encryption and decryption to meet data security needs. CebaTech’s hardware implementation of AES is in the form of a standalone soft core that implements the Rijndael algorithm as specified by NIST in FIPS PUB 197. AES is a symmetric key block cipher that works by encrypting blocks of 128 bits. The core supports three different key lengths - 128 bits, 192 bits and 256 bits as specified in the standard.
  • GunZip Data Inflate Core, based upon the same software code base for the very popular GZIP software program. CebaTech's GunZip is compatible with both hardware and software generated GZIP compressed files. CebaTech offers a single core that operates at approximately 2Gbps rates.
  • GZIP Data Deflate Core base upon the same software code used for the very popular GZIP software program. CebaTech's GZIP is standards-based and conforms to the popular "deflate" standard as specified in RFC1951. File formats for both ZLIB and GZIP, as specified in RFC1950 and 1952, are also supported. CebaTech offers a single core that can achieve rates up to 2 Gbps and that can be "tiled" to operate at higher aggregated stream rates of 8Gbps.
  • CebaTech's LZRW3 cores, are a direct hardware embodiment of Ross Williams’ original software implementation, enabling a state of the art FPGA or ASIC solution for wire-speed lossless data compression and decompression. CebaTech’s hardware implementation of LZRW3 is in the form of standalone soft cores that perform the compress and expand functions.
  • CebaTech's MD5 cores, are a direct hardware embodiment of Ron Rivest’s original software implementation as defined in RFC 1321, enabling a state of the art FPGA or ASIC solution for cryptographic hash function with 128-bit hash value. CebaTech’s hardware implementation of MD5 is in the form of standalone soft cores that perform the cryptographic hash function. CebaTech’s MD5 cores precisely follow the data formats defined by the software algorithm. CebaTech's MD5 cores are designed to reduce the processing overhead of high‐speed data hashing.
  • CebaTech's SHA-1 cores, are a direct hardware embodiment of NIST’s original software implementation as defined in FIPS PUB 180-1, enabling a state of the art FPGA or ASIC solution for cryptographic hash function with 160-bit hash value. CebaTech’s hardware implementation of SHA-1 is in the form of standalone soft cores that perform the cryptographic hash function. CebaTech’s SHA-1 cores precisely follow the data formats defined by the software algorithm. CebaTech's SHA-1 cores are designed to reduce the processing overhead of high‐speed data hashing.
  • CebaTech's SHA-256 cores, are a direct hardware embodiment of NIST’s original software implementation as defined in FIPS PUB 180-2, enabling a state of the art FPGA or ASIC solution for cryptographic hash function with 256-bit hash value. CebaTech’s hardware implementation of SHA-256 is in the form of standalone soft cores that perform the cryptographic hash function. CebaTech’s SHA-256 cores precisely follow the data formats defined by the software algorithm. CebaTech's SHA-256 cores are also designed to reduce the processing overhead of high‐speed data hashing.