C2R Compiler™

CebaTech's approach to ESL, the C2R Compiler™, incorporates standard, untimed ANSI C and automatically generates Verilog™ RTL. What makes it unique is that it couples the high level ANSI C design to the generated RTL, with the one absolutely and precisely reflecting the function of the other, to the benefit of the verification process.

Using conditional directives that reflect hardware macro-architecture in sequential C source code, the C2R Compiler produces hardware micro-architecture. At the same time, the source code maintains compatibility with any standard C compiler — a key capability that allows designers to leverage standard software development tools to accelerate functional verification of hardware designs.

The C2R Compiler overcomes the "semantic chasm" between sequential software models and parallel hardware design through complete support of the ANSI C language in a threads environment. Not only does this enable rapid implementation of original designs, it also allows IC designers to derive hardware from existing and proven software with relative ease.

By automating the development path from standard ANSI C code to synthesizable RTL, and sustaining the direct linkage between original design model and final hardware instantiation, a design flow based on the C2R Compiler provides:

  • ANSI C support spanning all data types: structs, unions, and complex arrays (with pointers and nesting, etc.)
  • A non-preemptive thread environment with scheduler to support concurrency
  • A linker that allows an entire system to be coded in C and that supports SoC design of any scope.
  • Support of both control and data path dominated designs
  • Equal support of FPGA, ASIC or SoC designs.
  • Cycle-accurate C (CAC) output that precisely represents the behavior of the compiled RTL in a simulator.
  • Rapid verification of designs (original C source or CAC) in a native C software environment with a standard C compiler (e.g., gcc).